`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Arizona State University
// Engineers: Brentton Garber, Georgii Tkachuk
// 
// Create Date: 17:28:56 05/01/2013 
// Design Name: CPU
// Module Name: CPU
// Project Name: Lab 3
// Target Devices: Xilinx Spartan6 XC6LX16-CS324 
// Tool versions: Xilinx ISE 14.2 
// Description: CPU contains a reg set, a decoder, and an ALU. It takes the input data,
//					 decrypts it, then executes the commands accordingly
//
// Revision: 1
// Revision 0.01 - File Created
//
//////////////////////////////////////////////////////////////////////////////////
module CPU(
	input [7:0] instr_data,
	input instr_exec,
	input clk,
	input reset,
	output [3:0]reg_data,
	input [1:0]dis_addr);
	
wire pop;
// delay the input data by a clock cycle
data_delay delay(.clk(clk),
	.i_pop(instr_exec),
	.o_pop(pop));
	 
wire LDR, SUM, CMP, MUL;
wire [3:0] data;
wire [1:0]addr;

// Initialize the instruction decoder module
instr_decoder id (
	.instr_data(instr_data),
	.clk(clk),
	.reset(reset),
	.instr_exec(pop),
	.o_data(data),
	.o_addr(addr),
	.alu_en(alu_en),
	.LDR(LDR),
	.SUM(SUM),
	.CMP(CMP),
	.MUL(MUL));
	

wire [3:0] rega;
wire [3:0] regb;
wire [7:0] ALU_data;

// Initialize the register set modules and connect it to the proper inputs
register_set rs (
	.data(data), 
	.addr(addr),
	.LDR(LDR),
	.dis_read(1'b1),
	.dis_addr(dis_addr),
	.alu_en(alu_en),
	.reset(reset),
	.clk(clk),
	.ALU_data(ALU_data),
	.rega(rega),
	.regb(regb),
	.dis_data(reg_data));

// Initialize the ALU module and connect it to the proper inputs
ALU alu(
	.CMP(CMP),
	.SUM(SUM),
	.MUL(MUL),
	.rega(rega),
	.regb(regb),
	.result(ALU_data));

endmodule
